1. Field of the Invention
The present invention relates to an etching apparatus and method and, more specifically, to a plasma etching apparatus and method for performing etching by generating a plasma with pulse modulation. The invention also relates to a manufacturing method of a semiconductor using such an etching apparatus or method, as well as to a semiconductor device manufactured by that method.
2. Background Art
In recent years, as the degrees of integration of semiconductor devices etc. increase, their densities have increased at high speed by miniaturization of patterns. Particularly in the technical fields of DRAMs, ASICs, etc. where vertically processed shapes of a half micron or less are required, etching techniques capable of high-precision processing are needed. The dry etching technique is widely used as one of such means.
FIG. 14 shows the configuration of a conventional RF-biased etching apparatus. This is an example of most typical dry etching techniques using an RF bias. In FIG. 14, reference numeral 1 denotes a reaction container for maintaining a vacuum. The pressure in the reaction container 1 is controlled by an evacuation outlet 2, a vacuum pressure indicator 3, and a vacuum pressure setting valve 4b. Flow rate controllers 4a cause etching gases such as Cl.sub.2 and BCl.sub.3 to be introduced into the reaction container 1 through gas introduction inlets 5 while controlling their flow rates. A semiconductor substrate as a sample 6 to be etched is held by one of two opposed electrodes 7 that form a capacitor. The opposed electrodes 7 are connected to a matching box 10 for a plasma impedance control and a high-frequency power supply 8. The high-frequency power supply 8 produces a sinusoidal voltage.
In this etching apparatus, negative charges are accumulated on the side of the sample-side one of the electrodes 7 that form a capacitor, because electrons supplied from a generated plasma are tens of times more than ions. Because of those capacitor charges, as shown in FIG. 15, a voltage that is shifted to the negative side appears on the semiconductor substrate as the sample 6 to be etched. Because of the presence of this negative voltage, positive ions as etching species are accelerated and strike the semiconductor substrate, to enable anisotropic etching. As disclosed in Japanese Unexamined Patent Publication Nos. 6-61182, 8-241885, 8-20880, etc., there have been invented dry etching methods that use a bias voltage having a pulse waveform.
In etching methods using a bias voltage having a pulse waveform, etching of a high selective ratio is possible and hence fine processing margins are increased. The term selective ratio as used above is defined by a ratio of the etching rate of a sample film to that of a photoresist for masking the sample film to be etched. However, since the rate of ion incidence on a sample film is low, the amount of reaction products that are produced from a photoresist and etching gases is small. Therefore, side wall protective films are thin in forming metal interconnections by etching the sample film. Accordingly, it is difficult to provide processed metal interconnections having good shapes due to side etching or roughening of side walls of interconnection.
Further, as disclosed in Japanese Unexamined Patent Publication No. 9-260359, there has been invented an etching method in which an etching gas of Cl.sub.2 and a deposition-type gas of CHF.sub.3 are used as well as a pulse waveform bias voltage is applied. However, this etching method possibly has problems that are fatal to an etched film from the viewpoint of recent etching techniques for fine processing. The problems are excess depositions of reactive products that are produced from CHF.sub.3 and ions such as Cl.sup.-, etching residues, short-circuiting of wiring, and shape differences due to pattern density differences in a film to be etched.